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RD151TS3312ARP, RD151TS3322ARP
Spread Spectrum Clock for EMI Solution
REJ03D0793-0100 Rev.1.00 May 11, 2006
Description
RD151TS3312ARP and RD151TS3322ARP is a high-performance Spread Spectrum Clock generator. It is suitable for EMI solution of electric systems.
Features
* Supports 10 MHz to 20 MHz operations. Multiple rate (XIN: SSCOUT) = 1: 1 Input frequency 10 MHz to 20 MHz * Spread spectrum modulation ; RD151TS3312ARP : 1.5%, 0.5% (Central spread modulation) RD151TS3322ARP : -3.0%, -1.0% (Down spread modulation)
Key Specifications
* * * *
*
Supply voltages: VDD = 3.3 V 0.3 V Cycle to cycle jitter = 100 ps typ. Clock output duty cycle = 50 5% Output slew rate = 0.7 V/ns typ. Ordering Information
Part Name Package Type SOP-8 pin (JEDEC) Package Code (Previous Code) PRSP0008DD-C (FP-8DCV) RP Package Abbreviation Taping Abbreviation (Quantity) H (2,500 pcs / Reel)
RD151TS3312ARPH0 RD151TS3322ARPH0
Block Diagram
VDD GND
NC XIN 1/M
R = 1 M
XOUT
OSC
Synthesizer 1/N SSC Modulator
SSCOUT
SEL
R = 350 k
SSN
Mode Control
R = 350 k
Rev.1.00 May 11, 2006 page 1 of 8
RD151TS3312ARP, RD151TS3322ARP
Pin Arrangement
XIN
1
8
VDD
XOUT
2
7
SEL
NC
3
6
SSCOUT
SSN
4
5
GND
(Top view)
Pin Descriptions
Pin name GND VDD NC SSCOUT XIN XOUT SEL SSN No. 5 8 3 6 1 2 7 4 Type Ground Power NC Output Input Output Input Input Description GND pin Power supply pin. Don't connect any VDD or GND. Spread spectrum modulated clock output. Oscillator input. Oscillator output. SSC% mode select pin. LVCMOS level input. Pull-down by internal resistor (350 k). SSC ON/OFF select pin. LVCMOS level input. Pull-down by internal resistor (350 k).
SSC Function Table
STB 0 0 1 1 Note: SEL 0 1 0 1 RD151TS3312ARP(Central spread) 1.5%*1 0.5% OFF RD151TS3322ARP(Down spread) -3.0%*1 -1.0% OFF
1. 1.5%(TS3312ARP) / -3.0%(TS3322ARP) SSC is selected for default by internal pull-down resistors.
Clock Frequency Table
PRODUCT RD151TS3312ARP RD151TS3322ARP XIN(MHz) 10 to 20 10 to 20 SSCOUT(MHz) 10 to 20 10 to 20 Multiply rate (XIN: SSCOUT) 1:1 1:1
Rev.1.00 May 11, 2006 page 2 of 8
RD151TS3312ARP, RD151TS3322ARP
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage *1 Input clamp current Output clamp current Continuous output current Maximum power dissipation Storage temperature Symbol VDD VI VO IIK IOK IO Tstg Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VDD+0.5 -50 -50 50 0.7 -65 to +150 Unit V V V mA mA mA W C Conditions
VI < 0 VO < 0 VO = 0 to VDD Ta = 55C (in still air)
Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Recommended Operating Conditions
Item Supply voltage DC input signal voltage High level input voltage Low level input voltage Input clock duty cycle Operating temperature Symbol VDD VIH VIL Ta Min 3.0 -0.3 0.7xVDD -0.3 45 -20 Typ 3.3 -- -- -- 50 -- Max 3.6 VDD+0.3 VDD+0.3 0.3xVDD 55 85 Unit V V V V % C Conditions
DC Electrical Characteristics
Ta = -20 to 85 C, VDD = 3.0 to 3.6 V
Item Input current Symbol II Min -- -- Input capacitance CI -- Typ -- -- 3 Max 20 100 -- pF Unit A Test Conditions VI = 0 V or 3.6 V, VDD = 3.6 V, XIN pin VI = 0 V or 3.6 V, VDD = 3.6 V, SEL, SSN pins SEL, SSN pins
DC Electrical Characteristics / SSC Clock Output
Ta = -20 to 85 C, VDD = 3.0 to 3.6 V
Item Output voltage Output current Output impedance Symbol VOH VOL IOH IOL Min VDD-0.2 -- -- -- -- Typ -- -- -13 13 40 Max -- 200 -- -- -- Unit V mV mA Test Conditions IOH = -1 mA IOL = 1 mA VOH = 1.5 V, VDD = 3.3 V VOL = 1.5 V, VDD = 3.3 V
Note: Parameters are target of design. Not 100% tested in production.
Rev.1.00 May 11, 2006 page 3 of 8
RD151TS3312ARP, RD151TS3322ARP
AC Electrical Characteristics / SSC Clock Output
Ta = 25C, VDD = 3.3 V, CL = 15 pF
Item Operating current Cycle to cycle jitter *1 Symbol IDD tCCS Min -- -- Typ 12 |100| Max 17 -- Unit mA ps Test Conditions VDD = 3.3 V, CL = 15 pF, XIN = 20 MHz SEL = 0, CL = 0 pF SSC = 1.5% (TS3312ARP) SSC = -3.0% (TS3322ARP) VDD = 3.3 V, 0.2 x VDD to 0.8 x VDD Notes
Figure 1
Slew rate
tSL
--
0.7
4.0
V/ns
Clock duty cycle 45 50 55 % Stabilization time *2 -- -- 2 ms Notes: Parameters are target of design. Not 100% tested in production. 1. Cycle to cycle jitter is included spread spectrum modulation. 2. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up.
SSCOUT
tcycle n
tcycle n+1
tCCS = (tcycle n) - (tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.1.00 May 11, 2006 page 4 of 8
RD151TS3312ARP, RD151TS3322ARP
Application Information
1. Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Figure 2. VDD decoupling is important to both reduce Jitter and EMI radiation. The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability.
XIN (Crystal or Reference input) XOUT (Crystal or Not connection) NC
1
8
C1
C2
VDD
2
7
SEL R1
GND GND
3
6
SSCOUT
SSN
4
5
GND
Notes:
C1 = High frequency supply decoupling capacitor. (0.1 F recommended) C2 = Low frequency supply decoupling capacitor. (22 F recommended) R1 = Match value to line impedance. Figure 2 Recommended circuit configuration
Rev.1.00 May 11, 2006 page 5 of 8
RD151TS3312ARP, RD151TS3322ARP 2. Example Board Layout Configuration
VDD (+3.3V Supply)
P FB
22 F
G
0.1 F Crystal connection or Reference input Crystal connection or No connection 1
G
2
7 R1
3
6
SSCOUT
4
5
G
Note:
G Via to GND plane R1 = Match value to line impedance. FB = Ferrite bead.
Figure 3 Example Board Layout
Rev.1.00 May 11, 2006 page 6 of 8
RD151TS3312ARP, RD151TS3322ARP 3. Example of TS33XX EMI Solution IC's Application
Spread Spectrum Modulated Clock XIN XOUT TS33XXA SSCOUT CPU & ASIC XTAL Memory Graphics System Cont. Ref. Clock 3.3 V CMOS level ref. Clock
Figure 4 Ref. Clock Input Example
Spread Spectrum Modulated Clock XIN XTAL XOUT TS33XXA SSCOUT CPU & ASIC Memory Graphics System Cont.
Figure 5 XTAL Ref. Clock Input Example
Rev.1.00 May 11, 2006 page 7 of 8
System BUS
System BUS
RD151TS3312ARP, RD151TS3322ARP
Package Dimensions
JEITA Package Code P-SOP8-3.95x4.9-1.27 RENESAS Code PRSP0008DD-C Previous Code FP-8DCV MASS[Typ.] 0.085g
*1
D 5
F
8
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE E
*2
Index mark
Terminal cross section ( Ni/Pd/Au plating )
1 Z e 4
*3
c
Reference Dimension in Millimeters Symbol
bp
x
M L1
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 4.90 5.30 3.95
0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0 8 5.80 6.10 6.20 1.27 0.25 0.10 0.75 0.40 0.60 1.27 1.08
Rev.1.00 May 11, 2006 page 8 of 8
A
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